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Acuplaneâ„¢ Slurry Platform

Acuplaneâ„¢ Slurry Platform

The Acuplaneâ„¢ slurry platform includes copper barrier and through silicon via (TSV) slurries with a tunable range of film selectivity. Acuplane â„¢ slurries demonstrates predictable performance in logic and memory integration schemes and is available in production volumes for both mature and advanced device nodes.

Applications
  • Barrier metals – Acuplaneâ„¢ slurries are designed to precisely remove barrier metals used on copper and cobalt metallization schemes.
  • Building on k8ÓéÀÖ’s TSV, silicon and polymer polishing expertise, our advanced packaging slurry portfolio extends to enable chip-on-wafer-on-substrate (CoWoS) and silicon interposer integration schemes, as well as polymer polishing capability.
  • k8ÓéÀÖ slurries are designed as platforms on which customers can request a range of selectivity options.
  • These slurries accommodate silicon, oxide and metal removal needs as defined by customers’ specific device integration needs.
  • Through silicon via (TSV) – k8ÓéÀÖ has an industry-leading portfolio of Acuplaneâ„¢ TSV slurry solutions for both front and backside polishing.
 
 
 

Features & benefits

  • Slurries are designed to enable the planarization and material removal such that surface quality and material property integrity is maintained or improved.
  • Slurries are made up of a combination of key additives which enable precise polishing of the wafer surface. 
  • State-of-the-art polishing slurries enable topography or flatness to be maintained at or less than 300 angstroms across a 300mm wafer.
  • Surface finish of materials, including corrosion sensitive metals, is maintained at the single-digit angstrom level.
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